TechForce :: SoC Physical Design















	Graphics SoC 65nm - Timing constraints, STA, chip-level clock scheme & skew analysis, IR drop of power grid Low Power Display ASIC 90nm - Block-level APR, timing closure, SI & IR, DRC / LVS Wireless Home Networking SoC 130nm - Block-level APR, Timing closure, DRC / LVS

	"TechForce Physical Design team helped us tape out our 90nm SoC on time. They have displayed a high level of commitment & professionalism during this project. Their expertise in timing closure and physical verification helped in saving a lot of time." Manager - Physical Design Leading fabless semiconductor company

With state-of-the-art design methodology, a highly skilled engineering team and a track record of successful tapeouts, TechForce has emerged as a leading provider of Physical Design services.

TechForce has exprience in technologies ranging from 65nm to 180nm. Our physical design team has taped out chips ranging from 500k gates to 25+ million gates at frequencies ranging from 200 MHz to 500+ Mhz.

Our physical design team is well versed in addressing physical design issues related to processes for leading pureplay foundries and IDMs. TechForce has extensive experience in all the leading physical design EDA tools including, Synopsys, Magma, Cadence and Mentor Graphics.

Our Physical Design capabilities include:

Physical synthesis
Static Timing Analysis (STA)
Hierarchical floorplanning and design partitioning
Place & Route
Physical optimization and timing closure
Signal integrity and power analysis
Low Power Optimization
Physical verification and chip finishing

For more information on how you can benefit from our Physical Design expertise, please email us to sales@tforceinc.com.